1. Field of the Invention
The present invention relates to a digital data record/replay device and more particularly to an apparatus for detecting a synchronization signal in a digital data record/replay device.
2. Description of Related Art
Typically, erroneously detected sync signals are removed using a fixed window with respect to detected sync signals. At this time, if errors occur in data or a sync signal pattern or if the number of clocks of a predetermined sync signal does not coincide with the number of clocks of an actual sync signal, the detected sync signals may be all missed.
FIG. 1 is a block diagram showing a configuration of a conventional apparatus for detecting a sync signal in a digital data record/replay device. The conventional apparatus includes: serial to parallel converter 11 for converting serial data, SDATA, and serial clocks, SCLK, which have been input as a result of reconstructing recorded data using an equalizer and phase locked loop (PPL), into parallel data, PDATA, and parallel clocks, PCLK; sync pattern detector 12 for comparing the parallel data, PDATA, and the parallel clocks, PCLK, received from the serial to parallel converter 11 with a predetermined sync pattern and for producing a pattern matching sync, SYNC_P, and a sync pattern detecting position signal, POSIT, according to a result of the comparison; window unit 13 for generating a window signal, WIN, for opening a window at regular intervals according to a track reference signal; comparator 14 for comparing the pattern matching sync, SYNC_P, output from the sync pattern detector 12 with the window signal, WIN, output from the window part 13 and outputting a sync signal, W_SYNC, according to a result of the comparison; first delay unit 15 for receiving the sync pattern detecting position signal, POSIT, from the sync pattern detector 12 and delaying the position signal until the sync signal, W_SYNC, of the comparator 14 is received; latch unit 16 for latching an output of the first delay unit 15 according to the sync signal, W_SYNC, of the comparator 14 and outputting the sync position signal; second delay unit 17 for delaying the parallel data, PDATA, from the serial to parallel converter 11 until the sync position signal is received; and re-sorting unit 18 for resorting and outputting the parallel data, PDATA, output from the second delay unit 17 according to the sync position signal output from the latch unit 16.
With reference to the accompanying drawings, operation of the conventional apparatus for detecting a sync signal in a digital data record/replay device will now be described.
Primarily, the serial to parallel converter 11 converts serial data, SDATA, and serial clocks, SCLK, which have been input as a result of reconstructing recorded data using an equalizer and phase locked loop (PPL), into parallel data, PDATA, and parallel clocks, PCLK and outputs the parallel data and clocks to the respective sync pattern detector 12 and second delay unit 17.
The sync pattern detector 12 then shifts the parallel data, PDATA, output from the serial to parallel converter 11 by one bit, divides the data into groups each consisting of the predetermined number of bits, and compares each group of bits with a predetermined sync signal pattern. If the data matches the predetermined sync signal pattern, the sync pattern detector 12 outputs a pattern matching sync, SYNC_P, to the comparator 14 and outputs a corresponding sync pattern detected position signal, POSIT, to the first delay unit 15.
The window unit 13 generates a window signal, WIN, to the comparator 14. The window signal is for opening a window at regular intervals according to a track reference signal. The window unit 13 is initialized by a reset signal, RESET, received from the latch unit 16.
The comparator 14 determines whether or not there is the pattern matching sync, SYNC_P, within the window signal, WIN. If there is the pattern matching sync, SYNC_P, the comparator 14 generates a sync signal, W_SYNC, to the latch unit 16.
The first delay unit 15 delays output of the sync pattern position signal, POSIT, from the sync pattern detector 12 to the latch unit 16 until the sync signal, W_SYNC, from the comparator 14 is input to the latch unit 16.
The latch unit 16 then latches the output of the first delay unit 15 and outputs the sync position signal to the re-sorting unit 18 in accordance with the sync signal, W_SYNC, received from the comparator 14.
The second delay unit 17 delays the parallel data from the serial to parallel converter 11 until the sync position signal is input to the re-sorting unit 18.
Subsequently, the re-sorting unit 18 re-sorts the parallel data output from the second delay unit 17 according to the sync position signal output from the latch unit 16 and produces re-sorted parallel data, RE_PDATA.
In such apparatus for detecting a sync signal in the digital data record/replay device according to the conventional art, the sync signal pattern which has been previously set during recording is a very important fact in detecting the sync signal. Damage in a tape, degradation of a signal, and an error in rotative velocity of a drum may interfere with right signal detection.
For example, there occur errors in the sync pattern or data pattern, or the number of clocks of a predetermined sync signal may not coincide with the number of clocks of an actual sync signal.
In the apparatus for detecting a sync signal in the digital data record/replay device according to the conventional art, a pulse generator (PG) signal or a head switching pulse (HSP) signal is used as the track reference signal which is used in the window unit 13 to prevent erroneous detection of the sync signal. These signals may have irregular errors and this may cause the window signal to deviate from a substantial position.
Accordingly, the present invention is directed to an apparatus for detecting a sync signal in a digital data record/replay device that substantially obviates one or more of the limitations and disadvantages of the related art.
An objective of the present invention is to solve the problem of deviation of a window caused by erroneous detection of a sync signal and disagreement of the numbers of clocks by using a specified window.
Additional features and advantages of the invention will be set forth in the following description, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure as illustrated in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, an apparatus for detecting a sync signal in a digital data record/replay device having a parallel clock generator, a parallel data generator, and a window unit comprises: a sync signal detector for comparing a pattern matching sync signal output from a sync pattern detector with an output signal of the window unit and detecting a sync signal according to clocks of the parallel clock generator; a latch unit for latching the sync signal detected by the sync signal detector and outputting the sync signal as a sync position signal according to clocks of the parallel clock generator; an identification error correction code (ID ECC) controller for generating an ID ECC control signal according to the sync position signal of the latch unit; an ID ECC decoder for decoding ID areas of parallel data generated by the parallel data generator; and a sync signal checking unit for outputting the sync position signal of the latch unit as a final sync signal and, when errors are detected as a result of the ID ECC decoding, sending a control signal to the window unit.
The sync signal checking unit outputs the sync position signal from the latch unit as a final sync signal only when an error is not detected as a result of the decoding by the ID ECC decoder.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.